1. Field of the Invention
This invention relates to magnetic storage systems and, more particularly, to data channels for processing signals read from a magnetic medium.
2. Description of the Related Art
During a write operation in a magnetic disk storage system, write current applied to a read-write head is modulated according to digital data to record a sequence of magnetic flux transitions in concentric tracks on a magnetic medium. In a subsequent read mode, the read-write head moving over the magnetic medium converts the magnetic transitions into an analog signal of alternating polarity. The analog signal is then detected and decoded in a read channel to reproduce the recorded digital data. While a simple peak detector may be used to detect the analog signal from the read-write head, discrete time sequence detectors that compensate for intersymbol interferences (ISI) are now employed to reduce susceptibility to noise and to increase storage capacity and reliability.
FIG. 1 illustrates a known detection and decoding arrangement using a discrete time sequence detector. In FIG. 1, there is a variable gain amplifier (VGA) 101, an analog to digital converter (ADC) 105, a finite impulse response (FIR) equalizer 110, a timing and gain control 115, a discrete time sequence detector 125 (e.g., a Viterbi detector), a decoder 128 and a host computer 130. During a read operation, a signal output of the read-write head is amplified in VGA 101 and the output of VGA 101 is converted into a sequence of timed samples in ADC 105. The sample sequence is equalized in FIR equalizer 110 and equalized sample sequence is supplied to the discrete time sequence detector 125 which provides time sequence detection. The detected sequence is then converted into digital data in the decoder 128 and the decoded digital data is supplied to the host computer 130.
As is well known, the FIR filter equalizer 110 in FIG. 1 employs a set of parameter signals to compensate for variations in magnetic and electrical characteristics over the magnetic disk, disk angle and environmental conditions. The output of the FIR equalizer 110 is also applied to the timing and gain control 115 which operates to provide signals for adjusting the timing of samples in the ADC 105 and the gain of the VGA 101. During the equalization of user data, the timing and gain control 115 receives the sample sequence output of the FIR equalizer 110 and provides signals to maintain proper amplitude in VGA 101 and proper timing for sampling of signals in the ADC 105. Prior to the user data reading, a preamble pattern is read to synchronize the sampling of the analog waveform in ADC 105 and to initially adjust the gain of the variable gain amplifier 101 using the FIR equalizer output.
FIG. 2 shows an exemplary FIR equalizer having an n tap delay that may be used in the circuit of FIG. 1. As shown in FIG. 2, the FIR equalizer includes delays 201-0 through 201-n+1, multipliers 205-0 through 205-n+1 and an adder 207. The output sample sequence from the ADC 105 in FIG. 1 is supplied to the input of the delay 201-0 and is sent through the serially arranged delays 201-0 through 201-n+1. The output of each delay is also applied to an associated one of multipliers 205-0 through 205-n+1 which multipliers also have equalizer coefficient inputs C0 through Cn+1, respectively, applied thereto. The values of the coefficients C0 through Cn+1 are previously determined from least mean square estimation obtained by having the FIR equalizer provide predetermined targets for a range of waveforms read from the magnetic disk. Arrangements for generating the FIR equalizer coefficients for least mean square (LMS) adaptive FIR filters are disclosed in xe2x80x9cDigital Baseband Transmission and Recordingxe2x80x9d, Jan W. M. Bergmans, Kiuwer Academic Publishers (ISBN 0-7923-9775-4).
In order to perform accurate equalization of a large range of input waveforms, an FIR equalizer having a large number of taps (e.g., 10-20) is required and the delay through or latency in the FIR equalizer may be 10 to 20 cycles or more. The tracking of the timing and gain by the timing and gain control 115 during reading of user data is not usually affected by the latency since the bandwidth for timing and gain changes during the data reading is ordinarily relatively low. In the initial acquisition period during which a synchronization pattern is read, however, large changes in timing and gain can be expected. These large changes require a high bandwidth timing and gain control loop. In the initial synchronization period of the read channel, the large latency in the FIR equalizer 110 having 10 to 20 delay taps operates to slow down the timing and gain adjustments and may cause instability.
U.S. Pat. No. 5,585,975 issued to William G. Bliss Dec. 17, 1996 discloses an equalization scheme for sample value estimation and sequence detection in a sampled amplitude read channel in which a pair of serially connected programmable discrete time filters equalizes signal samples into desired equalization. The first equalizer estimates sample values and a second equalizer provides for sequence detection of digital data. The timing and gain control loop for the equalization scheme includes the first equalizer that operates during both the preamble and user data segments of a sector signal so that long latency in the first equalizer adapted to equalize user data waveforms affects the timing and gain loop bandwidths during the preamble segment.
U.S. Pat. No. 5,903,857 issued to Richard T. Behrens et al. May 11, 1999 discloses an arrangement for calibrating an analog filter in a sampled amplitude read channel wherein an analog filter precedes an analog to digital converter in a series circuit having a discrete equalizer FIR filter. A timing recovery loop includes the FIR filter used for both preamble and user data so that the FIR filter latency affects the timing loop operation. Accordingly, there is a problem in providing rapid and stable synchronization in read channels having multi-tap FIR filter equalizers adapted to equalize a wide range of waveforms.
The invention is directed to a data channel for processing a signal from a storage medium in which a timed sample sequence is formed in response to the storage medium signal. A filtering unit equalizes the timed sample sequence in response to a set of parameter signals and a control unit controls the forming of the timed sample sequence in response to the equalized time sample sequence from the filtering unit.
According to the invention, a first filtering unit equalizes the timed sample sequence during a first signal segment in response to a first number of parameter signals and a first control unit controls forming of the timed sample sequence in the first signal segment. A second filtering unit equalizes the timed sample sequence during a second signal segment in response to a second number of parameter signals and a second control unit controls forming of the timed sample sequence in the second signal segment.
According to one aspect of the invention, the number of first parameter signals is smaller than the number of second parameter signals.
According to another aspect of the invention, each first parameter signal is a linear combination of at least some of the second parameter signals.
According to yet another aspect of the invention, the first filtering unit and the second filtering unit both provide substantially the same equalized timed sample sequence for the signal of the first signal segment.
According to yet another aspect of the invention, the number of first parameter signals is at least two.
According to yet another aspect of the invention, the second parameter signals includes a set of second FIR equalizer coefficient signals c0, c1, c2, . . . cn, cn+1 and the first parameter signals includes a set of first FIR equalizer coefficient signals K0=f(c0, c2, c4, . . . cn,), K1=f(c1, c3, c5, . . . cn+1).
According to yet another aspect of the invention, the first FIR equalizer coefficient signals which form substantially the same equalized timed sample sequence as the second FIR equalizer coefficients for the signal of the first signal segment are
K0=c0xe2x88x92c2+c4xe2x88x92c6 . . . +cnxe2x88x922xe2x88x92cn
K1=c1xe2x88x92c3+c5xe2x88x92c7 . . . +cnxe2x88x921xe2x88x92cn+1.
According to yet another aspect of the invention, the first FIR equalizer coefficient signals K0 and K1 are formed in an initial portion of the first signal segment.
According to yet another aspect of the invention, the first signal segment includes a 4T sinusoid pattern and the timed sample sequence during the first signal segment includes a sequence of samples having values (s0, s1, xe2x88x92s0, xe2x88x92s1, . . . ). The target output equalized timed signal sequence of the first FIR equalizer for the first signal segment is of the form (xo, x1, xe2x88x92x0, xe2x88x92x1, . . . ). The first FIR equalizer coefficient signals that provide substantially the same response as the second FIR equalizer filter to the first signal segment are set to be k0=(K0*x1+K1*x0)/(x0*x0+x1x1) and k1=(K1*x1+K0*x0)/(x0*x0+x1x1).
According to yet another aspect of the invention, the timed sample sequence forming unit includes an amplifier and a sampling unit. The first control unit is responsive to the equalized timed sample sequence from the first filtering unit to control the gain of the amplifier and the timing of the sampling unit during the first signal segment and second control unit is responsive to the equalized timed sample sequence from the second filtering unit to control the gain of the amplifier and the timing of the sampling unit during the during the second signal segment.
In an embodiment of the invention, a signal from a read/write head amplified in a variable gain amplifier is periodically sampled in an analog-to-digital converter to form a time sample sequence. During a preamble segment of the signal, an first FIR filter equalizes the time sample sequence in response to a first set of FIR coefficients and first timing and gain control units control the gain of the variable gain amplifier and the timing of the sampling in response to the equalized preamble output of the first FIR filter. In a data segment of the signal, a second FIR filter equalizes the time sample sequence in response to a second set of FIR coefficients. Second timing and gain control units control the gain of the variable gain amplifier and the sampling in response to the equalized data output of the second FIR filter. The second set of FIR coefficients for the data segment are c0, c1, c2, . . . cn, cn+1. The first set of FIR coefficients for the preamble segment are K0=c0xe2x88x92c2+c4xe2x88x92c6 . . . +cnxe2x88x922xe2x88x92cn and K1=c1xe2x88x92c3+c5xe2x88x92c7 . . . +cnxe2x88x921xe2x88x92cn+1 to provide substantially the same equalized time sample sequence as the second set of FIR coefficients for the preamble segment. The FIR equalizer coefficient signals K0 an K1 are formed in the initial portion of the preamble segment.
In another embodiment of the invention, the preamble segment includes a 4T sinusoid pattern in which the timed sample sequence has a sequence of values (s0, s1, xe2x88x92s0, xe2x88x92s1, . . . ). The target output equalized timed sample sequence of the first FIR filter for the preamble signal segment is (xo, x1, xe2x88x92x0, xe2x88x92x1, . . . ) and the first FIR equalizer coefficient signals that provide substantially the same response as the second FIR equalizer filter to the preamble signal segment are set to be k0=(K0*x1+K1*x0)/(x0*x0+x1x1) and k1=(K1*x1+K0*x0)/(x0*x0+x1x1) during an initial portion of the preamble segment. The FIR equalizer coefficient signals k0 and k1 are formed in the initial portion of the preamble segment.
A fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.